1. Field of the Invention
The present invention generally relates to multilayer interconnection boards, and more specifically, to a multilayer interconnection board wherein a via forming part is used for interlayer connection.
2. Description of the Related Art
Recently and continuingly, high density mounting of electronic components such as semiconductor devices, for example, ICs (Integrated Circuits) or LSIs (Large Scale Integrations), is progressing. Because of this, the number of outside connection terminals provided at the electronic components is made large and pitches of the outside connection terminals are made narrow. Accompanying this, high density mounting of the electronic components on the multilayer interconnection board or a multilayer interconnection board structured with a large number of layers is progressing. See, for example, Japanese Laid-Open Patent Application No. 2003-163458.
FIG. 1 is a three-dimensional cross-sectional view of a related art multilayer interconnection board 1. FIG. 2 is a cross-sectional view of the related art multilayer interconnection board 1 shown in FIG. 1.
As shown in FIG. 1 and FIG. 2, a multilayer interconnection board 1 has a structure where plural insulation layers 2 made of, for example, glass epoxy are stacked. A wiring layer 3 is formed in each of the insulation layers 2 in a designated pattern. The wiring layers 3 are interlayer-connected by via forming parts 5. The via forming part 5 is formed by forming a piercing hole forming part in the insulation layer 2 and a conductive metal such as copper (Cu) is formed inside the piercing hole forming part.
However, resin such as epoxy resin is a main ingredient of the insulation layer 2 of the multilayer interconnection board 1. In addition, the via forming part 5 is formed of a conductive metal such as copper (Cu). Hence, the coefficient of thermal expansion of the insulation layer 2 is different from the coefficient of thermal expansion of the via forming part 5. Because of this, for example, if heat is applied to the multilayer interconnection board 1 when an electronic component and others are mounted, for example, difference of the coefficients of thermal expansion between the insulation layer 2 and the via forming part 5 is generated.
If the difference of the coefficients of thermal expansion between the insulation layer 2 and the via forming part 5 is generated, stress is generated inside the multilayer interconnection board 1.
FIG. 3 is a view showing a result of simulation for explaining the maximum strain generated due to the stress in the related art multilayer interconnection board 1.
As shown in FIG. 3, stress is easily generated in the vicinity of the center of the multilayer interconnection board 1. In addition, stresses are frequently generated at parts where diameters of lower end parts of the via forming parts 5 are narrow, namely a part indicated by an arrow A in FIG. 3. When the stress is concentrated on the lower end part of the via forming part 5, plastic strain is generated at this part. If such a plastic strain is further increased, a crack may be generated in the via forming part 5 or the via forming part 5 may be delaminated in a connection position.